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| MCP6241/2/4 50 A, 550 kHz Rail-to-Rail Op Amp Features * * * * * * Gain Bandwidth Product: 550 kHz (typ.) Supply Current: IQ = 50 A (typ.) Supply Voltage: 1.8V to 5.5V Rail-to-Rail Input/Output Extended Temperature Range: -40C to +125C Available in 5-pin SC-70 and SOT-23 packages Description The Microchip Technology Inc. MCP6241/2/4 operational amplifiers (op amps) provide wide bandwidth for the quiescent current. The MCP6241/2/4 has a 550 kHz Gain Bandwidth Product (GBWP) and 68 (typ.) phase margin. This family operates from a single supply voltage as low as 1.8V, while drawing 50 A (typ.) quiescent current. In addition, the MCP6241/2/4 family supports rail-to-rail input and output swing, with a common mode input voltage range of VDD + 300 mV to VSS - 300 mV. These op amps are designed in one of Microchip's advanced CMOS processes. Applications * * * * * * Automotive Portable Equipment Photodiode (Transimpedance) Amplifier Analog Filters Notebooks and PDAs Battery-Powered Systems Package Types MCP6241 SOT-23-5 VOUT 1 VSS 2 VIN+ 3 - + MCP6241 PDIP, SOIC, MSOP 5 VDD NC 1 VIN- 2 4 VIN- VIN+ 3 VSS 4 - + 8 NC 7 VDD 6 VOUT 5 NC Available Tools * SPICE Macro Models (at www.microchip.com) * FilterLab(R) Software (at www.microchip.com) MCP6241R MCP6242 PDIP, SOIC, MSOP VOUTA 1 VINA 2 _ Typical Application RG2 VIN2 RG1 VIN1 VDD RX RY RZ - MCP6241 + VOUT RF VOUT 1 VDD 2 VIN+ 3 SOT-23-5 5 VSS - + + - 8 VDD -+ +7 VOUTB 6 VINB_ 5 VINB+ 4 VIN- VINA+ 3 VSS 4 MCP6241U SC-70-5, SOT-23-5 VIN+ 1 VSS 2 VIN- 3 5 VDD MCP6244 PDIP, SOIC, TSSOP VOUTA 1 VINA- 2 14 VOUTD - + + - 13 VIND- 12 VIND+ 11 VSS 10 VINC+ - + +- 9 V - INC 8 VOUTC 4 VOUT VINA+ 3 VDD 4 Summing Amplifier Circuit VINB+ 5 VINB- 6 VOUTB 7 (c) 2005 Microchip Technology Inc. DS21882C-page 1 MCP6241/2/4 1.0 ELECTRICAL CHARACTERISTICS Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings VDD - VSS ........................................................................7.0V All Inputs and Outputs ................... VSS - 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD - VSS| Output Short Circuit Current ..................................continuous Current at Input Pins ....................................................2 mA Current at Output and Supply Pins ............................30 mA Storage Temperature.....................................-65C to +150C Maximum Junction Temperature (TJ) .......................... +150C ESD Protection On All Pins (HBM;MM) ............... 4 kV; 300V DC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, RL = 100 k to VDD/2 and VOUT VDD/2. Parameters Input Offset Input Offset Voltage Extended Temperature Input Offset Drift with Temperature Power Supply Rejection Input Bias Current and Impedance Input Bias Current: At Temperature At Temperature Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode Common Mode Input Range Common Mode Rejection Ratio Open-Loop Gain DC Open-Loop Gain (large signal) Output Maximum Output Voltage Swing Output Short-Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note: VDD IQ 1.8 30 -- 50 5.5 70 V A IO = 0, VCM = VDD - 0.5V VOL, VOH VSS + 35 ISC ISC -- -- -- 6 23 VDD - 35 -- -- mV mA mA RL = 10 k, 0.5V Output Overdrive VDD = 1.8V VDD = 5.5V AOL 90 110 -- dB VOUT = 0.3V to VDD - 0.3V, VCM = VSS VCMR CMRR VSS - 0.3 60 -- 75 VDD + 0.3 -- V dB VCM = -0.3V to 5.3V, VDD = 5V IB IB IB IOS ZCM ZDIFF -- -- -- -- -- -- 1.0 20 1100 1.0 1013||6 1013||3 -- -- -- -- -- -- pA pA pA pA ||pF ||pF TA = +85C TA = +125C VOS VOS VOS/TA PSRR -5.0 -7.0 -- -- -- -- 3.0 83 +5.0 +7.0 -- -- mV mV VCM = VSS TA= -40C to +125C, VCM = VSS (Note) Sym Min Typ Max Units Conditions V/C TA= -40C to +125C, VCM = VSS dB VCM = VSS The SC-70 package is only tested at +25C. DS21882C-page 2 (c) 2005 Microchip Technology Inc. MCP6241/2/4 AC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. Parameters AC Response Gain Bandwidth Product Phase Margin Slew Rate Noise Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Eni eni ini -- -- -- 10 45 0.6 -- -- -- VP-P nV/Hz fA/Hz f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz GBWP PM SR -- -- -- 550 68 0.30 -- -- -- kHz V/s G = +1 Sym Min Typ Max Units Conditions TEMPERATURE CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND. Parameters Temperature Ranges Extended Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 5L-SC70 Thermal Resistance, 5L-SOT-23 Thermal Resistance, 8L-MSOP Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note: JA JA JA JA JA JA JA JA -- -- -- -- -- -- -- -- 331 256 206 85 163 70 120 100 -- -- -- -- -- -- -- -- C/W C/W C/W C/W C/W C/W C/W C/W TA TA TA -40 -40 -65 -- -- -- +125 +125 +150 C C C (Note) Sym Min Typ Max Units Conditions The internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150C. (c) 2005 Microchip Technology Inc. DS21882C-page 3 MCP6241/2/4 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 100 k to VDD/2 and CL = 60 pF. 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% 90 CMRR, PSRR (dB) Percentage of Occurrences 630 Samples VCM = VSS 85 PSRR (VCM = VSS) 80 75 CMRR (VCM = -0.3V to +5.3V, VDD = 5.0V) -50 -25 0 25 50 75 Ambient Temperature (C) 100 125 70 -5 -4 -3 -2 -1 0 1 2 3 4 Input Offset Voltage (mV) 5 FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Temperature. 120 Open-Loop Gain (dB) CMRR, PSRR vs. Ambient 110 100 PSRR, CMRR (dB) 90 80 70 60 50 40 30 20 10 1.E+01 100 1.E+02 1k 10k 1.E+03 1.E+04 Frequency (Hz) 100k 1.E+05 PSRR+ PSRRCMRR 0 Gain Open-Loop Phase () RL = 10.0 k VCM = VDD/2 -30 -60 Phase -90 -120 -150 -180 -210 100 1k 10k 1.E+ 1M 1.E+ 1.E+ 1.E+ 1.E+ 100k 1.E+ 10M Frequency (Hz) 05 06 07 02 03 04 100 80 60 40 20 0 -20 0.1 1 10 1.E- 1.E+ 1.E+ 01 00 01 FIGURE 2-2: Frequency. 25% Percentage of Occurrences 20% 15% 10% 5% 0% 0 6 PSRR, CMRR vs. FIGURE 2-5: Frequency. 30% 25% 20% 15% 10% 5% 0% 0.0 0.2 0.4 180 Samples VCM = VDD/2 TA = +125C Open-Loop Gain, Phase vs. Percentage of Occurrences 180 Samples VCM = VDD/2 TA = +85C 0.6 0.8 1.0 1.2 1.4 1.6 1.8 Input Bias Current (pA) Input Bias Current (nA) FIGURE 2-3: Input Bias Current at +85C. FIGURE 2-6: Input Bias Current at +125C. DS21882C-page 4 (c) 2005 Microchip Technology Inc. 2.0 12 18 24 30 36 42 MCP6241/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 100 k to VDD/2 and CL = 60 pF. 10,000 Input Noise Voltage Density (nV/ Hz) 1,000 100 10 0.1 1 10 100 1k 10k 100k 1.E-01 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 Frequency (Hz) 0 1 2 3 4 5 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% Percentage of Occurrences 628 Samples VCM = VSS TA = -40C to +125C -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 Input Offset Voltage Drift (V/C) FIGURE 2-7: vs. Frequency. 300 Input Offset Voltage (V) Input Noise Voltage Density FIGURE 2-10: Input Offset Voltage Drift. 700 Input Offset Voltage (V) VDD = 1.8V 200 100 0 -100 -200 -300 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 TA = -40C TA = +25C TA = +85C TA = +125C 650 600 550 500 450 400 350 300 VDD = 1.8V VCM = VSS VDD = 5.5V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) Common Mode Input Voltage (V) FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. 400 Input Offset Voltage (V) VDD = 5.5V 300 200 100 0 -100 -200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -0.5 6.0 Common Mode Input Voltage (V) TA = -40C TA = +25C TA = +85C TA = +125C FIGURE 2-11: Output Voltage. 35 30 25 20 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 Input Offset Voltage vs. Short Circuit Current (mA) +ISC TA = +125C TA = +85C TA = +25C TA = -40C -ISC 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature. (c) 2005 Microchip Technology Inc. DS21882C-page 5 12 MCP6241/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 100 k to VDD/2 and CL = 60 pF. 0.50 0.45 Slew Rate (V/s) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 -50 -25 0 25 50 75 100 Ambient Temperature (C) 125 Time (1 s/div) VDD = 1.8V Rising Edge Falling Edge FIGURE 2-13: Temperature. 1,000 Output Voltage Headroom (mV) Slew Rate vs. Ambient FIGURE 2-16: Pulse Response. 5.0 4.5 Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Output Voltage (10 mV/div) VDD = 5.5V G = +1 V/V RL = 10 k Small-Signal, Non-Inverting VDD = 5.0V G = +1 V/V 100 VDD - VOH VOL - VSS 10 1 10 1.E-02 100 1m 1.E-01 1.E+00 Output Current Magnitude (A) 10m 1.E+01 Time (10 s/div) FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. 10 Max. Output Voltage Swing (VP-P) VDD = 5.5V VDD = 1.8V FIGURE 2-17: Pulse Response. 80 70 Quiescent Current per Amplifier (A) 60 50 40 30 20 10 0 Large-Signal, Non-Inverting VCM = 0.9VDD 1 TA = +125C TA = +85C TA = +25C TA = -40C 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) 0.1 1k 1.E+03 10k 100k 1.E+04 1.E+05 Frequency (Hz) 1M 1.E+06 FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-18: Quiescent Current vs. Power Supply Voltage. DS21882C-page 6 (c) 2005 Microchip Technology Inc. MCP6241/2/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps). TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP6241 (SOT-23-5) 1 4 3 5 2 -- MCP6241R (SOT-23-5) 1 4 3 2 5 -- MCP6241U (SOT-23-5) 4 3 1 5 2 -- Symbol VOUT VIN- VIN+ VDD VSS NC Description Analog Output Inverting Input Non-inverting Input Positive Power Supply Negative Power Supply No Internal Connection MCP6241 (PDIP, SOIC, MSOP) 6 2 3 7 4 1, 5, 8 TABLE 3-2: MCP6242 1 2 3 8 5 6 7 -- -- -- 4 -- -- -- PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS MCP6244 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol VOUTA VINA- VINA+ VDD VINB+ VINB- VOUTB VOUTC VINC- VINC+ VSS VIND+ VIND- VOUTD Description Analog Output (op amp A) Inverting Input (op amp A) Non-inverting Input (op amp A) Positive Power Supply Non-inverting Input (op amp B) Inverting Input (op amp B) Analog Output (op amp B) Analog Output (op amp C) Inverting Input (op amp C) Non-inverting Input (op amp C) Negative Power Supply Non-inverting Input (op amp D) Inverting Input (op amp D) Analog Output (op amp D) 3.1 Analog Outputs 3.3 Power Supply (VSS and VDD) The output pins are low-impedance voltage sources. 3.2 Analog Inputs The positive power supply (VDD) is 1.8V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single-(positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need a local bypass capacitor (typically 0.01 F to 0.1 F) within 2 mm of the VDD pin. These parts can share a bulk capacitor (typically 1 F to 100 F) with other nearby analog parts; it needs to be within 100 mm of the VDD pin. The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents. (c) 2005 Microchip Technology Inc. DS21882C-page 7 MCP6241/2/4 4.0 APPLICATION INFORMATION - RIN VIN MCP624X + VOUT The MCP6241/2/4 family of op amps is manufactured using Microchip's state-of-the-art CMOS process and is specifically designed for low-power and generalpurpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP6241/2/4 ideal for battery-powered applications. 4.1 Rail-to-Rail Inputs ( Maximum expected VIN ) - V DD RIN -----------------------------------------------------------------------------2 mA V SS - ( Minimum expected V IN ) R IN --------------------------------------------------------------------------2 mA The MCP6241/2/4 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 4-1 shows the input voltage exceeding the supply voltage without any phase reversal. 6 Input, Output Voltage (V) 5 4 3 2 1 0 -1 Time (1 ms/div) VIN VOUT VDD = 5.0V G = +2 V/V FIGURE 4-2: Resistor (RIN). Input Current-Limiting 4.2 Rail-to-Rail Output The output voltage range of the MCP6241/2/4 op amps is VDD - 35 mV (max.) and VSS + 35 mV (min.) when RL = 10 k is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-14 for more information. 4.3 Capacitive Loads FIGURE 4-1: Phase Reversal. The MCP6241/2/4 Show No The input stage of the MCP6241/2/4 op amps use two differential input stages in parallel. One operates at low common mode input voltage (VCM) and the other at high VCM. With this topology, the device operates with VCM up to 300 mV above VDD and 300 mV below VSS. The Input Offset Voltage is measured at VCM = VSS - 300 mV and VDD + 300 mV to ensure proper operation. Input voltages that exceed the input voltage range (VSS - 0.3V to VDD + 0.3V at 25C) can cause excessive current to flow into or out of the input pins. Current beyond 2 mA can cause reliability problems. Applications that exceed this rating must be externally limited with a resistor, as shown in Figure 4-2. Driving large capacitive loads can cause stability problems for voltage-feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +1) is the most sensitive to capacitive loads, but all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 70 pF when G = +1), a small series resistor at the output (RISO in Figure 4-3) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. - VIN MCP624X + RISO VOUT CL FIGURE 4-3: Output resistor, RISO stabilizes large capacitive loads. Figure 4-4 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the signal gain are equal. For inverting gains, GN is 1 + |Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). DS21882C-page 8 (c) 2005 Microchip Technology Inc. MCP6241/2/4 4.6 1.E+04 10k Recommended RISO ( ) PCB Surface Leakage 1k 1.E+03 GN = +1 V/V GN +2 V/V In applications where low input bias current is critical, PCB (printed circuit board) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6241/2/4 family's bias current at 25C (1 pA, typ.). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-6. VINVIN+ VSS 100 1.E+02 10p 100p 1n 10n 1.E+01 1.E+02 1.E+03 1.E+04 Normalized Load Capacitance; CL/GN (F) FIGURE 4-4: Recommended RISO Values for Capacitive Loads. After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Evaluation on the bench and simulations with the MCP6241/2/4 SPICE macro model are very helpful. Modify RISO's value until the response is reasonable. 4.4 Supply Bypass Guard Ring With this op amp, the power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good highfrequency performance. It can use a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other nearby analog parts. FIGURE 4-6: for Inverting Gain. 1. Example Guard Ring Layout 4.5 Unused Op Amps An unused op amp in a quad package (MCP6244) should be configured as shown in Figure 4-5. Both circuits prevent the output from toggling and causing crosstalk. Circuit A can use any reference voltage between the supplies, provides a buffered DC voltage, and minimizes the supply current draw of the unused op amp. Circuit B minimizes the number of components, but may draw a little more supply current for the unused op amp. 2. 1/4 MCP6244 (A) VDD VDD 1/4 MCP6244 (B) VDD Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the common mode input voltage. Inverting Gain and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. FIGURE 4-5: Unused Op Amps. (c) 2005 Microchip Technology Inc. DS21882C-page 9 MCP6241/2/4 4.7 4.7.1 Application Circuits MATCHING THE IMPEDANCE AT THE INPUTS 4.7.2 COMPENSATING FOR THE PARASITIC CAPACITANCE To minimize the effect of offset voltage in an amplifier circuit, the impedances at the inverting and noninverting inputs need to be matched. This is done by choosing the circuit resistor values so that the total resistance at each input is the same. Figure 4-7 shows a summing amplifier circuit. RG2 VIN2 RG1 VIN1 VDD RX RY RZ - MCP624X + VOUT RF In analog circuit design, the PCB parasitic capacitance can compromise the circuit behavior; Figure 4-8 shows a typical scenario. If the input of an amplifier sees parasitic capacitance of several picofarad (CPARA, which includes the common mode capacitance of 6 pF, typical) and large RF and RG , the frequency response of the circuit will include a zero. This parasitic zero introduces gain peaking and can cause circuit instability. VAC + MCP624X - RG RF VOUT VDC CPARA CF RG C F = CPARA * -----RF FIGURE 4-7: Summing Amplifier Circuit. To match the inputs, set all voltage sources to ground and calculate the total resistance at the input nodes. In this summing amplifier circuit, the resistance at the inverting input is calculated by setting VIN1, VIN2 and VOUT to ground. In this case, RG1, RG2 and RF are in parallel. The total resistance at the inverting input is: 1 R VIN - = -------------------------------------------1 1 1 --------- + --------- + ----- R G1 R G2 RF Where: RVIN- = total resistance at the inverting input At the non-inverting input, VDD is the only voltage source. When VDD is set to ground, both RX and RY are in parallel. The total resistance at the non-inverting input is: 1 R VIN + = ------------------------ + R Z 1 1 ------ + ----- RX RY Where: RVIN+ = total resistance at the inverting input To minimize offset voltage and increase circuit accuracy, the resistor values need to meet the condition: R VIN + = R VIN - FIGURE 4-8: Effect of Parasitic Capacitance at the Input. One solution is to use smaller resistor values to push the zero to a higher frequency. Another solution is to compensate by introducing a pole at the point at which the zero occurs. This can be done by adding CF in parallel with the feedback resistor (RF). CF needs to be selected so that the ratio CPARA:CF is equal to the ratio of RF:RG . DS21882C-page 10 (c) 2005 Microchip Technology Inc. MCP6241/2/4 5.0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6241/2/4 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6241/2/4 op amps is available on our web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation at room temperature. See the macro model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab(R) Software Microchip's FilterLab software is an innovative tool that simplifies analog active-filter (using op amps) design. Available at no cost from our web site at www.microchip.com, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. (c) 2005 Microchip Technology Inc. DS21882C-page 11 MCP6241/2/4 6.0 6.1 PACKAGING INFORMATION Package Marking Information 5-Lead SC-70 (MCP6241U Only) Example: XXN (Front) YWW (Back) OR XXNN AT2 (Front) 546 (Back) OR Example: AT25 5-Lead SOT-23 5 4 Device MCP6241 MCP6241R MCP6241U BRNN BSNN Code BQNN 5 4 XXNN 1 2 3 BQ25 1 2 3 Note: Applies to 5-Lead SOT-23. 8-Lead MSOP XXXXXX YWWNNN Example: 6242E 546256 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP6242 E/P e3 ^^256 0546 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Example: MCP6242E e3 SN^^ 0546 256 Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS21882C-page 12 (c) 2005 Microchip Technology Inc. MCP6241/2/4 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6244) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN MCP6244 e3 E/P^^ 0546256 14-Lead SOIC (150 mil) (MCP6244) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP6244 e3 E/SL^^ 0546256 14-Lead TSSOP (MCP6244) Example: XXXXXXXX YYWW NNN 6244E 0546 256 (c) 2005 Microchip Technology Inc. DS21882C-page 13 MCP6241/2/4 5-Lead Plastic Small Outline Transistor Package (LT) (SC-70) E E1 D p B n 1 Q1 c A1 L Units Dimension Limits n p A A2 A1 E E1 D L Q1 c B INCHES NOM 5 .026 (BSC) MILLIMETERS* NOM 5 0.65 (BSC) 0.80 0.80 0.00 1.80 1.15 1.80 0.10 0.10 0.10 0.15 A2 A MIN MAX MIN MAX Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Top of Molded Pkg to Lead Shoulder Lead Thickness Lead Width .031 .031 .000 .071 .045 .071 .004 .004 .004 .006 .043 .039 .004 .094 .053 .087 .012 .016 .007 .012 1.10 1.00 0.10 2.40 1.35 2.20 0.30 0.40 0.18 0.30 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEITA (EIAJ) Standard: SC-70 Drawing No. C04-061 DS21882C-page 14 (c) 2005 Microchip Technology Inc. MCP6241/2/4 5-Lead Plastic Small Outline Transistor (OT) (SOT23) E E1 p B p1 D n 1 c A A2 L A1 Number of Pins Pitch p1 Outside lead pitch (basic) Overall Height A .035 .057 0.90 Molded Package Thickness A2 .035 .051 0.90 Standoff A1 .000 .006 0.00 Overall Width E .102 .118 2.60 Molded Package Width E1 .059 .069 1.50 Overall Length D .110 .122 2.80 Foot Length L .014 .022 0.35 Foot Angle 0 10 0 c Lead Thickness .004 .008 0.09 Lead Width B .014 .020 0.35 Mold Draft Angle Top 0 10 0 Mold Draft Angle Bottom 0 10 0 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. EIAJ Equivalent: SC-74A Drawing No. C04-091 Units Dimension Limits n p MIN INCHES* NOM 5 .038 .075 .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5 MAX MIN MILLIMETERS NOM 5 0.95 1.90 1.18 1.10 0.08 2.80 1.63 2.95 0.45 5 0.15 0.43 5 5 MAX 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 (c) 2005 Microchip Technology Inc. DS21882C-page 15 MCP6241/2/4 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 A c A1 (F) A2 L Number of Pins Pitch A .043 Overall Height A2 .030 .037 Molded Package Thickness .000 .006 A1 Standoff E Overall Width E1 Molded Package Width D Overall Length L .016 .031 Foot Length Footprint (Reference) F Foot Angle 0 8 c Lead Thickness .003 .009 .009 .016 Lead Width B Mold Draft Angle Top 5 15 5 15 Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-187 Drawing No. C04-111 Units Dimension Limits n p MIN INCHES NOM 8 .026 BSC .033 .193 TYP. .118 BSC .118 BSC .024 .037 REF .006 .012 - MAX MIN MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0 0.08 0.22 5 5 - MAX 1.10 0.95 0.15 0.80 8 0.23 0.40 15 15 DS21882C-page 16 (c) 2005 Microchip Technology Inc. MCP6241/2/4 8-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A A2 c L A1 eB B1 p B Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB MIN INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10 MAX MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 .170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 (c) 2005 Microchip Technology Inc. DS21882C-page 17 MCP6241/2/4 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A A2 L A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX MIN .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21882C-page 18 (c) 2005 Microchip Technology Inc. MCP6241/2/4 14-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A A2 c eB A1 B1 B p L Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width .240 .250 .260 E1 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MIN MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 (c) 2005 Microchip Technology Inc. DS21882C-page 19 MCP6241/2/4 14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A A2 L A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX MIN .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 MAX 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 DS21882C-page 20 (c) 2005 Microchip Technology Inc. MCP6241/2/4 14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP) E E1 p D 2 n B 1 A c L A1 A2 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B1 MIN INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 MAX MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 (c) 2005 Microchip Technology Inc. DS21882C-page 21 MCP6241/2/4 NOTES: DS21882C-page 22 (c) 2005 Microchip Technology Inc. MCP6241/2/4 APPENDIX A: REVISION HISTORY Revision C (March 2005) The following is the list of modifications: 1. 2. Added the MCP6244 quad op amp. Re-compensated parts. Specifications that change are: Gain Bandwidth Product (BWP) and Phase Margin (PM) in AC Electrical Characteristics table. Corrected plots in Section 2.0 "Typical Performance Curves". Added Section 3.0 "Pin Descriptions". Added new SC-70 package markings. Added PDIP-14, SOIC-14, and TSSOP-14 packages and corrected package marking information (Section 6.0 "Packaging Information"). Added Appendix A: "Revision History". 3. 4. 5. 6. Revision B (August 2004) Revision A (March 2004) * Original Release of this Document. (c) 2005 Microchip Technology Inc. DS21882C-page 23 MCP6241/2/4 NOTES: DS21882C-page 24 (c) 2005 Microchip Technology Inc. MCP6241/2/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Tape and Reel and/or Alternate Pinout MCP6241: MCP6241T: MCP6241RT: MCP6241UT: MCP6242: MCP6242T: MCP6244: MCP6244T: -X /XX Examples: a) b) c) d) Extended Temp., 8LD SOIC package. MCP6241-E/MS: Extended Temp., 8LD MSOP package. MCP6241-E/P: Extended Temp., 8LD PDIP package. MCP6241RT-E/OT: Tape and Reel, Extended Temp., 5LD SOT-23 package MCP6241UT-E/OT: Tape and Reel, Extended Temp., 5LD SOT-23 package. MCP6241UT-E/LT: Tape and Reel, Extended Temp., 5LD SC-70 package. MCP6242-E/SN: MCP6242-E/MS: MCP6242-E/P: MCP6242T-E/SN: Extended Temp., 8LD SOIC package. Extended Temp., 8LD MSOP package. Extended Temp., 8LD PDIP package. Tape and Reel, Extended Temp., 8LD SOIC package. Extended Temp., 14LD PDIP package. Extended Temp., 14LD SOIC package. Extended Temp., 14LD TSSOP package. Tape and Reel, Extended Temp., 14LD SOIC package. Tape and Reel, Extended Temp., 14LD TSSOP package. MCP6241-E/SN: Temperature Package Range Device: Single Op Amp (MSOP, PDIP, SOIC) Single Op Amp (Tape and Reel) (MSOP, SOIC, SOT-23) Single Op Amp (Tape and Reel) (SOT-23) Single Op Amp (Tape and Reel) (SC-70, SOT-23) Dual Op Amp Dual Op Amp (Tape and Reel) (MSOP, SOIC) Quad Op Amp Quad Op Amp (Tape and Reel) (SOIC, TSSOP) e) f) Temperature Range: E = -40C to +125C a) b) c) d) Package: LT MS P OT Plastic Package (SC-70), 5-lead (MCP6241U only) Plastic Micro Small Outline (MSOP), 8-lead Plastic DIP (300 mil Body), 8-lead, 14-lead Plastic Small Outline Transistor (SOT-23), 5-lead (MCP6241, MCP6241R, MCP6241U) SN = Plastic SOIC (150 mil Body), 8-lead SL = Plastic SOIC (150 mil Body), 14-lead ST = Plastic TSSOP (4.4 mil Body), 14-lead = = = = a) b) c) MCP6244-E/P: MCP6244-E/SL: MCP6244-E/ST: d) MCP6244T-E/SL: e) MCP6244T-E/ST: (c) 2005 Microchip Technology Inc. DS21882C-page 25 MCP6241/2/4 NOTES: DS21882C-page 26 (c) 2005 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2005 Microchip Technology Inc. DS21882C-page 27 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Qingdao Tel: 86-532-502-7355 Fax: 86-532-502-7205 ASIA/PACIFIC India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 Japan - Kanagawa Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459 EUROPE Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 France - Massy Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Ismaning Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 England - Berkshire Tel: 44-118-921-5869 Fax: 44-118-921-5820 03/01/05 DS21882C-page 28 (c) 2005 Microchip Technology Inc. |
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